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Altera_Forum
Honored Contributor
Honored ContributorUse Stratix II PLL to generate clock with deviations and jitter?
Hi, after reading the documentation about dynamic reconfiguration of Stratix II PLLs, altpll and altpll_reconfig, I believe that it is possible to use such PLL to generate a clock signal (e.g....
Altera_ForumHonored Contributor
Honored ContributorOkay, the phase reconfiguration works fine. I'm able to "pull" a 25 MHz clock slightly up or down, max 1300 ppm. That's better than any VCXO that I could use.
For (some kind of) jitter I now consider to switch between several clocks (derived from the same base with different phase offset). The switching would have to occur in the exact middle between transistions. We'll see if that works... BTW, Is there some "standard" way to implement some kind of delay line without doing manual placement/routing? Thanks for your answers Kolja
