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I'm using my EPM1270T144C5 to implement a sinc3 filter to get my delta-sigma ADC result, and send the result to a DSP through it's external bus. As a result, I get two clock in my design one for the bus from a crystal and the other from the ADC's MCLK. Is that ok I use the two clock or I have to treat the MCLK signal as a logic input and use my high frequency clock to synchonous the MCLK signal?
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Probably not. It will depend on the flow from the ADC to the DSP. For example, does the DSP respond fast enough all the time, or could there be a delay sometimes?
Generally you would use a dual-clock FIFO. If the DSP could insert wait-states, then you would size the FIFO for the worst-case wait. Unfortunately you are using a CPLD that does not have internal memory, so implementing a FIFO will be expensive, i.e., it will use logic cells.
Here's a good article on clock-domain crossing ...
http://www.edn.com/design/systems-design/4333702/crossing-the-abyss-asynchronous-signals-in-a-synchronous-world If your ADC samples are really slow, then perhaps a simpler solution would work.
Cheers,
Dave
Honored Contributor
