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Probably not. It will depend on the flow from the ADC to the DSP. For example, does the DSP respond fast enough all the time, or could there be a delay sometimes?
Generally you would use a dual-clock FIFO. If the DSP could insert wait-states, then you would size the FIFO for the worst-case wait. Unfortunately you are using a CPLD that does not have internal memory, so implementing a FIFO will be expensive, i.e., it will use logic cells.
Here's a good article on clock-domain crossing ...
http://www.edn.com/design/systems-design/4333702/crossing-the-abyss-asynchronous-signals-in-a-synchronous-world If your ADC samples are really slow, then perhaps a simpler solution would work.
Cheers,
Dave
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The DSP read the bus every 62.5us and I get my ADC result updated every 25.6 us. Is there anyway that I could get my right ADC result without changing my cpld device? Thank you for your help.
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