Use HPS DDR3 Memory from FPGA address question

Hi, i´m following this example to have ddr3 memory available to the Fabric on the DE0 nano soc.

I write to hps ddr3 with a write master and modular scatter gather DMA.

https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/writing_to_hps_memory

The first is to tell linux from uboot for reduce their memory usage for example from 1gb to 512mb its trivial.

But i don´t undersand how the HPS 2 FPGA SDRAM INTERFACE manages the addresses.For example if it adds some kind of offset.

If i write to the address (1 073 741 824 ) / 2 is my data being written just at the beginning of the second 512 mb ram 0X20000000 ?

I´m developing some drivers to output linux video to an adv7123 and adv 7511 hdmi and audio to a wm8731 and because the nano doesn´t have ddr on the fabric i will use this approach to use for the buffering stuff.