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Altera_Forum's avatar
Altera_Forum
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16 years ago

Use conf.done pin

I am using a Cyclone-IV device which is configured as a combination of a NIOS-II and other logic units. "NIOS II reset" is an input signal to reset the NIOS-II processor inside the FPGA. In ad...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Yes. correct. I don't know of any way to internally read the CONF_DONE or INIT_DONE lines. If doesn't really make sense you see. If your FPGA is up and running, then obviously you are configured and initialized. So normally we use an internal reset generator circuit that becomes active after initialization to reset internal logic (like the NIOS).

Jake