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Altera_Forum
Honored Contributor
Honored ContributorUse conf.done pin
I am using a Cyclone-IV device which is configured as a combination of a NIOS-II and other logic units. "NIOS II reset" is an input signal to reset the NIOS-II processor inside the FPGA. In ad...
Altera_ForumHonored Contributor
Honored ContributorWhat I usually do is run the optional INIT_DONE line through an external reset generator to generate the reset signal for my logic.
However, you can and should also have an internal reset generator circuit for your logic. Here are some threads to look at: http://www.alteraforum.com/forum/showthread.php?t=6602&referrerid=2226 http://www.alteraforum.com/forum/showthread.php?t=6621&referrerid=2226 Jake
