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Altera_Forum's avatar
Altera_Forum
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16 years ago

Use conf.done pin

I am using a Cyclone-IV device which is configured as a combination of a NIOS-II and other logic units. "NIOS II reset" is an input signal to reset the NIOS-II processor inside the FPGA. In ad...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I don't think it is possible to use CONF_DONE as a reset, because the usermode is entered after CONF_DONE is released. So when entering the useremode, this signal is High per definition (if pulled up, it is open collector). See fig 8-16 and table 8-10 of the Cyclone IV handbook.

Maybe you can feed this signal through a delay circuit on your PCB and use the output of this circuit as a reset-signal for your logic.

Good luck, Ton