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Altera_Forum
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14 years ago

USB Blaster VCC

Hello :)

I'd like a quick confirmation about the USB Blaster. I'm implementing my design on a PCB, and I've to make a connector to programm my FPGA with the USB Blaster.

So I decided to programm my FPGA with JTAG (is it a good choice? Will I be able to programm my FPGA like this?), made a connector on my PCB, and connected TCK, TDO, TMS, TDI and the two GND according the USB Blaster User guide.

But I don't know how to connect VCC: is it the VCC of the IO (in my case: 3.3V), or the VCCint? (So, 1.2V for the cyclone 3...)

Thanks in advance,

ParalaX

14 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    I decided to programm my FPGA with JTAG (is it a good choice? Will I be able to programm my FPGA like this?)

    --- Quote End ---

    Yes you can program your FPGA with JTAG. Whether it is a good choice depends on what else is on your board. For example, will your board need to configure itself without having to use JTAG?

    --- Quote Start ---

    But I don't know how to connect VCC: is it the VCC of the IO (in my case: 3.3V), or the VCCint? (So, 1.2V for the cyclone 3...)

    --- Quote End ---

    The VCC on the JTAG header determines the voltage of the JTAG signals. The FPGA determines the requirements for these signals. You need to read the handbook associated with your FPGA to determine which bank determines the JTAG signal voltage requirements, and then use the same voltage as the VCCIO for that bank. For example, if your I/Os are all using 3.3V, then the JTAG VCC will be 3.3V.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    And by the way, do you know if ebay's cheap copy of the USB Blaster are functional?

    --- Quote End ---

    According to the link:

    "The mini USB Blaster is another variation of original official altera USB-Blaster. It is based on Cy7C68013 MCU, which use firmware to emulate the FT232BL protocol and drivers and is compatible with original USB-Blaster."

    So this version is based on a similar approach to this:

    http://fpga4u.epfl.ch/wiki/fx2

    based on some reverse engineering performed by Kolja Waschk (kawk)

    http://ixo-jtag.sourceforge.net/

    http://sourceforge.net/apps/mediawiki/urjtag/index.php?title=cable_altera_usb-blaster

    Ask the UrJTAG list whether they have used this cable.

    I suspect that it will work fine.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    As far as using JTAG as a programming sequence, that's fine, and I recommend the having the JTAG header, but programming the FPGA this way will not stick, unless you also support some other means of programming. (IE Active Serial, Passive Serial, etc).

    IE It will loose the programming at every power cycle unless you program a flash device to hold the programming.

    For Systems with an external CPU, we tend to use either passive serial or passive parallel programming mode.

    For systems with no CPU we tend to use Active Serial mode. In this case, we have the "Active Serial" header and the JTAG header so we can program the Active serial device directly. This can be bypassed through JTAG, but it's more complicated, to do it that way.

    As far as a USB Blaster compatible device, we've had good luck from Terasic's programmer.

    http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=74

    Regards,

    Pete
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thanks a lot to everyone for your informations!

    I'll see if I can do AS and JTAG on my board (since I don't have much room for it), but otherwise I'll juste use JTAG and reprogram the FPGA every time. It's no big deal since it's a development board :)

    ParalaX
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    ParalaX;

    I know that you mentioned that you just have a development board. However, in the future, if you want to be able to program both the FPGA and a Flash chip such as an EPCS16, where you have the combined programming of both (using jtag indirect configuration file .jic) then you will want to make sure to have the JTAG header VCC at 2.5 V.

    -James
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I recently had a board (just this week) where I had 3.3V hooked up to VCC pin on the JTAG header for a PCB. The JTAG header was for programming the EP3C5 part and EPCS16 through indirect jtag configuration. The 3.3V on the VCC pin of the JTAG header was a mistake in the schematic that propagated to the PCB. However, since the board had controlled impedance & stackup, I thought I would go ahead and try to make the board work. The FPGA programmed about 3 times, then after that, it quit. I could recognize the FPGA through the JTAG pins in the Quartus programmer, but could not program it. I've put 2.5V on all JTAG VCC header pins before this, and indeed this PCB issue confirms that 2.5 is essential. I know that you can use clamping diodes if you use 3.3V, but this seems to be extra components when simply using 2.5V will work. I am curious if anyone has consistently designed the JTAG header at VCC of 3.3V and had the FPGA successfully program time after time? With or without clamping diodes?

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I'm using 3.3V but I'm using buffers between the JTAG header and the FPGA pins, and no clamping diodes since the buffer is quite close to the FPGA.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Daixiwen; That is quite interesting. Are the output of the buffers at 3.3V? Did you put any series resistance in between the buffer and the FPGA? What type of bugger did you use, a standard type 244 or similar? Thanks, James

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hey James,

    Here's a design with lots of JTAG buffers/tricks in it, feel free to ask questions;

    http://www.ovro.caltech.edu/~dwh/carma_board/gda06rb004_carma_v0.87_dec03.pdf

    Page 7 has a high-level overview. Look on the front page for the other locations of JTAG stuff, eg., page 44, 77, 78, 79. Some of the FPGA outputs are 2.5V, and they're run into 3.3V buffers, mainly so that the LEDs are on bright enough. The TinyLogic buffers are cheap and convenient to place and route on a PCB.

    Cheers,

    Dave