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I'm not going to put a PS header on the board, that would be a bit goofy wouldn't it? As I said, it's only for development, so I'm going to stick some short flywires down and connect them to a header until I can get the micro to load the FPGA.
This being the case, I still don't have an answer to my original question. Why does the Cyclone III manual say to connect the USB Blaster to VCCA instead of VCCIO?
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Read the handbook for details:
http://www.altera.com/literature/hb/cyc3/cyclone3_handbook.pdf p165 "Configuration and JTAG Pin I/O Requirements"
- lots of warnings about overshoot on the JTAG signals
- be careful your flying leads do not have ringing on them
p206: "The TDO output pin is powered by VCCIO in I/O bank 1. All the JTAG input pins are powered by the VCCIO pin. All the JTAG pins support only LVTTL I/O standard."
p207: "Because JTAG pins do not have the internal PCI clamping diodes to prevent voltage overshoot when using VCCIO of 2.5, 3.0, and 3.3 V, you must power up the VCC of the download cable with a 2.5-V supply from VCCA, and you must pull TCK to ground."
Altera recommend you use VCCA = 2.5V so that the USB-Blaster cable drives 2.5V logic levels, which if they over-shoot provide a little more margin than if you'd powered the cable from 3.3V. A robust board design would actually include buffers right at the 10-pin header so that the USB-Blaster signals are not directly driving the FPGA pins.
In your case, measure the signals with a scope. If you source terminate your flying leads, you should be able to eliminate ringing.
Cheers,
Dave
Honored Contributor
