Forum Discussion
6 Replies
- Altera_Forum
Honored Contributor
do you have enough fractional bits in your signal?
and no, don't use float. without seeing the rest of your code we cant say what's wrong. - Altera_Forum
Honored Contributor
- Altera_Forum
Honored Contributor
How do you know in which step of the calculation the result is set to zero? I can't guess without knowing the component code.
- Altera_Forum
Honored Contributor
- Altera_Forum
Honored Contributor
The code has several length matching errors and doesn't compile. Also, what's the fpdiv component?
Assignments with length msimatch: p<= to_sfixed(i)*data_in; b<= (i*Pi); cv_q<=to_slv(b); - Altera_Forum
Honored Contributor
@ fvm sir,
ihave taken i (2 downto 0,data_in (14 bits),so in multiplication result is 16 bits. as i take i an ufixednumber,so i convert in in sfixed. now i take pi (ufixed(2 downto -7) ) so after multiplication it should be 6 downto -7,but i take b(b:ufixed(8 downto -8);) to match with the fixed point division 16 bit inputs. yep there is error,u r right,i will use correct range, other else.............. sir.