Upgrade Altera Cyclone II fpga device

Question

Hallo,

i use a Cyclone II EP2C35F484C8 device. We always have problems with overload of CPU. The TimeQuest Timing Analyzer reports timing problems of the CPU takt (required: 120MHz, actually: 83,45MHz).

I made synthesis with other device (EP2C35F484C6). The TimeQuest Timing Analyzer reports then 112,75MHz of CPU takt.

My Question:

Is upgrade from EP2C35F484C8 to EP2C35F484C6 possible? Are the pins 100% compatible?

Thank you for the answers.

altera_forum · Answer

It will be pin compatible, but you might try adding pipeline stages in your SOPC fabric first (assuming SOPC and not Q-sys).  I have been able to get C8 speed grade up to 100MHz without too much trouble, I'm not too sure about 120MHz, but it might be possible.

altera_forum · Answer

Hello kosh271,  thanks for your answer.   "you might try adding pipeline stages in your sopc fabric first" Do you mean NIOS II settings in SOPC? In my design the NIOS is set to NIOS II/f. It runs with 120MHz. There may however sometimes overload. I think, the choice of other device of this series with higher speed grade may resolve this problem.  Are there other disadvantages to the use of EP2C35F484C6?

altera_forum · Answer

Consider adding pipeline bridge.

altera_forum · Answer

Have a look in the Timequest report for the top failing paths, and it is usually possible to add Avalon pipeline bridges to improve timing.

One of the first things I do is to add one between the Nios' instruction and data masters and the JTAG debug module. This modification alone usually gives a big improvement on FMax.

altera_forum · Answer

Thanks for the answers.   How can I add the "Avalon-MM pipeline bridges"? I only see "Avalon Tristate Bridge" under "Avalon Components -&gt; Bridges" in SoPC builder . I use Quartus 10.0sp1.

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Upgrade Altera Cyclone II fpga device

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