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Honored Contributor
Honored ContributorUpgrade Altera Cyclone II fpga device
Hallo, i use a Cyclone II EP2C35F484C8 device. We always have problems with overload of CPU. The TimeQuest Timing Analyzer reports timing problems of the CPU takt (required: 120MHz, actually: ...
Altera_ForumHonored Contributor
Honored ContributorHave a look in the Timequest report for the top failing paths, and it is usually possible to add Avalon pipeline bridges to improve timing.
One of the first things I do is to add one between the Nios' instruction and data masters and the JTAG debug module. This modification alone usually gives a big improvement on FMax.
