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Altera_Forum
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15 years ago

Unwanted inference of RAMs

I am working with an SOPC system design that includes a custom UART component. In the VHDL design of this component, I specify a memory using: type fifo_type is array (0 to NUMWORDS-1) of std_l...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Can you use code tags next time you post code please :)

I compiled it with and without a reset. I get an M4K (I used a Cyclone 1) with no reset and logic when there is a reset. When I made a reset signal stuck at '0', it also placed an M4K, so I can only assume your reset is set to '0'.