Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Unwanted inference of RAMs

I am working with an SOPC system design that includes a custom UART component. In the VHDL design of this component, I specify a memory using: type fifo_type is array (0 to NUMWORDS-1) of std_l...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I have tried to the global synthesis rules. If my UART is its own project, the global settings work, as do the attribute statements. When the UART is taken as a component within the SOPC, these things no longer work.

within the VHDL that instantiates the memory, fifo_sig is the correct name.

here is an exerpt from the fitter report (reformatted) when the RAM is extracted:

|UART_TOP:UART_TOP_0| --> |fifo_sync:FIFO_SYNC_RX| --> |altsyncram:fifo_sig_rtl_0| --> |altsyncram_iog1:auto_generated| --> M4Ks = 1