Unused REFCLK and GXB Pins

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Is there any reason why I can't connect all of these pins directly to GND, especially that they are all of them strictly input pins.

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The logic levels on these pins are not ground referenced, i.e. the input common mode voltage, Vicm, is not zero. Use a resistor.

Cheers,

Dave

That makes perfect sense then.

Thanks Dave!

10K resistors avoids additional current consumption, if the input OCT is activated. It's also said, that the 10K resistors should be placed near to the inputs. How many resistors are used is a matter of most convenient routing, I think.

An interesting point with the transceiver and reference clock input termination suggestions is that they give up the idea of a differential DC bias for unused receivers, that has been e.g. recommended for Arria in datasheet updates. I hope, that Altera engineers don't reveal belatedly an excessive current consumption as they did in the previous case.

That's interesting because I just saw in one of the Cyclone IV demo boards, they tied both REFCLKn and REFCLKp together directly to ground.

Thinking more about it, I don't believe those pins have any OCT because you are required to put the termination outside (page 1-28 of the device handbook.)

The OCT issue still exists with the GXB_RX pins though.

Does this sound like a correct reasoning?

I don't have a lot a space on my board and I am wondering if I can use only 2 x 10k resistors.

I would like to use use 1 resistor per bank (QL0, QL1) to connect all unused GXB_RXn, GXB_RXp together?

Is it possible ? Or each signal type needs it own resistor ?

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I don't have a lot a space on my board and I am wondering if I can use only 2 x 10k resistors.

I would like to use use 1 resistor per bank (QL0, QL1) to connect all unused GXB_RXn, GXB_RXp together?

Is it possible ? Or each signal type needs it own resistor ?

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Look at a few of the Altera reference designs and see what they do there.

For example, on the Stratix IV GX Development Kit schematic, page 8, I see that they have tied p+n together from 5 REFCLK channels (10 pins) through to ground using a single 10k resistor. They have then tied the p+n channel from a single receiver channel to ground through a 10k resistor.

In this particular case, I'm not sure that they have separated the REFCLK from the receiver channel because that is a requirement, I think they've used two 10K resistors for reasons of physical layout, since the pin numbers look like the pins might be on different sides of the FPGA. You'd have to take a more detailed look at the pin planner view of the FPGA to confirm that hypothesis.

Cheers,

Dave