New Contributor
Regular ContributorHi,
You can follow the guidelines inside the document. If you are using FHT channel, then connect the pins as per suggested.
New ContributorMy questions are on unclear statements on guideline.
13A and 13C has separate supply and ENB_GXF_FHT inputs. We are using All FHT13C but not using any FHT13A Rx/Tx. Guide line says if there is no FHT channel used. Given this fact can we connect 13A supplies and ENB_GXF_FHT input to GND?
Should we connect I_PIN_PERST_N_GXF to GND if F Tile is used but not as PCIE ? This is not directly specified.
Another question is on recovery clock output from F tiles. Is there a specific reason to have them as output from clk pins instead of routing them through fabric ? This is a question to minimize test connector cnt on out design If we can route the recovery clk through fabric I will mux recovery clk from multiple links inside FPGA and observe them on a single external connector. Is there a rule for their pin assignment when used for links with more than 4 differential pairs? Is it at the same frequency with the data rate or with the reference clk input? Is it LVDS?
