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Altera_Forum
Honored Contributor
Honored ContributorUnunderstood error message
Hello, I am working on a VHDL project using the Altera DK-N2EVAL-3C25N development kit which is a NIOS II CYCLONE III environment. While proceeding with the "Start Analysis & Elaboration" menu, ...
Altera_ForumHonored Contributor
Honored ContributorHi alaaayed:
the port or signal SCLK is not declared in your design. The SCLK that you describe from the fsm module is the name of the port internal in the module but is not known in audio_project. To solve the problem, you should add the definition of the SCLK signal.
