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Honored Contributor
Honored ContributorUninitialized value of a signal in vhdl
This may be a noob vhdl question, but I have stuck at this point! Consider the following codes (a test bench which uses a detector and write entities). Since the reset signal (r) is set to 1, I expec...
Altera_ForumHonored Contributor
Honored ContributorFirst of all - I would do two things and retest:
1. Have we assigned in only a single process - otherwise you'll get multiple driver problems 2. remove the initial value of r. You're setting it at time 0 anyway.
