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Altera_Forum's avatar
Altera_Forum
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8 years ago

Uninitialized value of a signal in vhdl

This may be a noob vhdl question, but I have stuck at this point! Consider the following codes (a test bench which uses a detector and write entities). Since the reset signal (r) is set to 1, I expec...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

First of all - I would do two things and retest:

1. Have we assigned in only a single process - otherwise you'll get multiple driver problems

2. remove the initial value of r. You're setting it at time 0 anyway.