Uninitialized value of a signal in vhdl

This may be a noob vhdl question, but I have stuck at this point! Consider the following codes (a test bench which uses a detector and write entities). Since the reset signal (r) is set to 1, I expect that we signal goes to 0 but the simulation shows that the value of we is u which means uninitialized. You may try this code!

entity test_tb is
end;
architecture x of test_tb is
    component test_detector port( clk: in std_logic;
                rst: in std_logic;
                count: in integer range 0 to 7;
            z: out integer range 0 to 7;
                we: out std_logic );
    end component;                      
    component test_write port( a: in integer range 0 to 7;     
                count: in integer range 0 to 7;
                oe: in std_logic;
                clk: in std_logic;
                z: out integer range 0 to 7);      
    end component;
    
    signal clk: std_logic := '0';      -- clock
    signal r: std_logic := '1';      -------------------------------------- reset is initialized to '1'
    signal count: integer range 0 to 7 := 2;    
    signal z, num: integer range 0 to 7;    
    signal we: std_logic;
begin
    u2: test_detector port map( clk, r, count, z, we );     
    u3: test_write port map( z, count, we, clk, num );
    process( clk )    
    begin
        clk <= not clk after 2 ns;
    end process;        
    process
    begin
     r <= '1';    ----------------------------  reset is '1'
    wait for 4 ns;
    r <= '0';
    wait;
    end process;
end;

entity test_detector is
    port( clk: in std_logic;
                rst: in std_logic;
                count: in integer range 0 to 7;
            z: out integer range 0 to 7;
                we: out std_logic );
end;
architecture my1 of test_detector is
begin
    process( rst )
    begin
        if  rst = '1' then          ----------- this condition is true
            we <= '0';             ------- we should be 0
        end if;
    end process;
    process( clk )    
    begin             
        if (clk'event and clk = '1') then
            if count = 1 then
                z <= 7;
                we <= '1';
            end if;
        end if;
    end process;    
end;

entity test_write is
    port( a: in integer range 0 to 7;     
                count: in integer range 0 to 7;
                oe: in std_logic;
                clk: in std_logic;
                z: out integer range 0 to 7);
end;
architecture behav of test_write is                
begin                                
    process( clk )
    begin
        if (clk'event and clk = '1' and oe = '1') then
            if (count < 7) then    
                z <= a; 
            end if;
        end if;
    end process;
end;