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FST's avatar
FST
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4 years ago

unexpected FPGA IO state during programming of the Serial Configuration Device via JTAG

Hi

We use Quartus19.1 to generate a .jbc file for the EPCS128 connected to a EP4CE6F17I7N FPGA via the Active Serial interface..

On our board we use the Jam STAPL Byte-Code Player Version 2.2 software to program the Serial Configuration Device via JTAG.

The programming is working, but propably during the time of access to the Serial Configuration Device via the Serial Flash Loader (SFL) some IOs of the FPGA do not have anymore this Weak Pull-ups as we expect.

(E.g. when I start programming the output (Pin B4) gets first input with weak Pull-up for a while and then just input or input with Weak Pull-down before it gets again ouput at the end.)

Is there any explanation of this behavior?

Best Regards

Fredi

P.S.

As I remember, we had similar effects in a old project, but only when we generated the .jbc file with Quartus newer then 13.1. Maybe that helps to find the problem.

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  • YuanLi_S_Intel's avatar
    YuanLi_S_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi Fendi,


    Sorry for being late, i was in discussion with internal team about this. From the timing diagram, it seems like the pin is pulled down during image file (JBC File) programming.


    Also, you mentioned that the JBC file generated after v13.0, all pin are pulled-up during programming, but now, when generated with v19.1, all pin are pulled-down during programming?


    Regards

    Bruce


    • FST's avatar
      FST
      Icon for New Contributor rankNew Contributor
      4 years ago

      Hi Bruce

      I do not know whether all Pins are low during programming of the Configuration Flash via JTAG and SFL Bridge. At least Pin R7 is it. Why? And can we change that?

      We have not tried this project with Quartus v13.1 yet. That was some years ago where we had similar issues. But maybe it was something else. I will ask your designer to try with Quartus v13.1.

      Is from your side something different between v13.1 and v19.0 according automatic added SFL Bridge?

      Regards

      Fredi

  • FST's avatar
    FST
    Icon for New Contributor rankNew Contributor
    4 years ago

    Hi Bruce

    Today we build the .jbc file once with Quartus 13.1 and once with 19.1.

    During the programming of the 13.1 file the Pin R7 has allways weak pull-up, during the programming of the 19.1 file the Pin R7 goes to low as mentioned before.

    So, what is the difference between 13.1 and 19.1 according the automatic added SFL bridge?

    Do we have to do something different?

    Regards

    Fredi