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FST
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4 years ago

unexpected FPGA IO state during programming of the Serial Configuration Device via JTAG

Hi We use Quartus19.1 to generate a .jbc file for the EPCS128 connected to a EP4CE6F17I7N FPGA via the Active Serial interface.. On our board we use the Jam STAPL Byte-Code Player Version 2.2 sof...
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FST
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4 years ago

Hi Bruce

Today we build the .jbc file once with Quartus 13.1 and once with 19.1.

During the programming of the 13.1 file the Pin R7 has allways weak pull-up, during the programming of the 19.1 file the Pin R7 goes to low as mentioned before.

So, what is the difference between 13.1 and 19.1 according the automatic added SFL bridge?

Do we have to do something different?

Regards

Fredi