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FST
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5 years ago

unexpected FPGA IO state during programming of the Serial Configuration Device via JTAG

Hi We use Quartus19.1 to generate a .jbc file for the EPCS128 connected to a EP4CE6F17I7N FPGA via the Active Serial interface.. On our board we use the Jam STAPL Byte-Code Player Version 2.2 sof...
FST's avatar
FST
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5 years ago

Hi Bruce

Here are the more detailed timing measurements. I added also the JTAG TCK signal.

The CONF_DONE is going 3 times to low during the whole programming process.

After the second time (see Detail B), where in my opinion the SFL is active, we get the problem with the user IO at Pin R7.

It stays low instead of high with weak pull-up.

With the reconfiuration in Detail C, Pin R7 gets again high with weak pull-up and then high driven by our user mode.

Regards

Fredi