Forum Discussion

FST's avatar
FST
Icon for New Contributor rankNew Contributor
4 years ago

unexpected FPGA IO state during programming of the Serial Configuration Device via JTAG

Hi We use Quartus19.1 to generate a .jbc file for the EPCS128 connected to a EP4CE6F17I7N FPGA via the Active Serial interface.. On our board we use the Jam STAPL Byte-Code Player Version 2.2 sof...
YuanLi_S_Intel's avatar
YuanLi_S_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Is it possible to show me the full timing diagram? There should be another CONF_DONE toggling after the bootup of actual image.