Forum Discussion

FST's avatar
FST
Icon for New Contributor rankNew Contributor
5 years ago

unexpected FPGA IO state during programming of the Serial Configuration Device via JTAG

Hi We use Quartus19.1 to generate a .jbc file for the EPCS128 connected to a EP4CE6F17I7N FPGA via the Active Serial interface.. On our board we use the Jam STAPL Byte-Code Player Version 2.2 sof...
FST's avatar
FST
Icon for New Contributor rankNew Contributor
5 years ago

Hi Bruce,

You might be right, but that's not our user mode. It's a kind of user mode when the Serial Flash Loader Bridge from Quartus 19.1 is loaded and active.

How are the IOs defined during this? Do we have to do it somewhere?

Best Regards

Fredi