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FST's avatar
FST
Icon for New Contributor rankNew Contributor
4 years ago

unexpected FPGA IO state during programming of the Serial Configuration Device via JTAG

Hi We use Quartus19.1 to generate a .jbc file for the EPCS128 connected to a EP4CE6F17I7N FPGA via the Active Serial interface.. On our board we use the Jam STAPL Byte-Code Player Version 2.2 sof...
YuanLi_S_Intel's avatar
YuanLi_S_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


I think the pin is toggled to low during user mode. The reason is the the CONF_DONE is pulled back to high to indicates that the configuration is done and is in user mode. Probably you might want to check your pin state in your design.


Regards,

Bruce