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FST's avatar
FST
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4 years ago

unexpected FPGA IO state during programming of the Serial Configuration Device via JTAG

Hi We use Quartus19.1 to generate a .jbc file for the EPCS128 connected to a EP4CE6F17I7N FPGA via the Active Serial interface.. On our board we use the Jam STAPL Byte-Code Player Version 2.2 sof...
YuanLi_S_Intel's avatar
YuanLi_S_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Yes, all unused pin in user mode can be define in this setting.


May i know what are you trying to show in thie pin R7? Can you please clarify?


  • FST's avatar
    FST
    Icon for New Contributor rankNew Contributor
    4 years ago

    Hi

    I'm sorry that I confused you. Actually it was always Pin R7 I talked about. We use this user output as Backlight-Enable signal in our design.

    The picture I attached, shows that this output R7 (trace C3) is going low (instead high with weak pull-up) in the programming phase when the configuration memory gets accessed via JTAG-SFL-ASMI. Visible because the Chipselect ouput 'CSO' of the FPGA (trace C2) is toggling.

    Before this phase of programming you can see that the output is high with weak pull-up. Which is as expected and I assume that this is the phase where the SFL bridge gets loaded to the FPGA via JTAG.

    At the beginn and at the end of the picture the output is high, when the FPGA is in user mode.

    Trace C1 is the CONF_DONE output of the FPGA.

    So, my question. Way gets the user output R7 low during programming?

    Regards

    Fredi