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FST
New Contributor
5 years agounexpected FPGA IO state during programming of the Serial Configuration Device via JTAG
Hi
We use Quartus19.1 to generate a .jbc file for the EPCS128 connected to a EP4CE6F17I7N FPGA via the Active Serial interface..
On our board we use the Jam STAPL Byte-Code Player Version 2.2 sof...
FST
New Contributor
5 years agoHi
See attached picture which shows the behavior according to Pin R7 of our FPGA.
Regards
Fredi