Hi, I am trying to figure out requirements for Dynamic Phase Alignment (DPA) as implemented by LVDS receiver (non-GXB) in Altera Stratix-II family. The device handbook provides very limited information: "the dpa block requires a training pattern and a training sequence of at least 256 repetitions of the training pattern. the training pattern is not fixed, so you can use any training pattern with at least one transition on each channel." I want to know a bit more than that. In particular: 1. Minimal training pattern length in bits 2. Maximal training pattern length in bits 3. Does Minimal/Maximal length depend on deserialization factor? 4. Are there limitations for minimal/maximal transition density? Did you, dear experts, see more detailed information on the issue or, may be, learned something about it from experience? Best Regards, Michael

In the last section of the handbook(all the timing numbers) there should be DPA specs.

--- Quote Start --- In the last section of the handbook(all the timing numbers) there should be DPA specs. --- Quote End --- There are specs in Chapter 5, but they don't answer my questions. For example, could long run of 10-bit "comma" patterns generated by one of the popular 8b/10b alphabets serve as DPA training sequence when deserialization factor=8 rather than 10? Chapter 5 gives no answer. To the contrary, the spec tables in Chapter 5 introduce yet another concept that I don't understand (and that handbook does not explain) - DPA run length. If there is no good answer to my questions above, may be, somebody here could answer a related question. What happens when DPA is presented with sequence of bits that is guaranteed to have certain density of transitions, for example, >10%, but is totally aperiodic? Does DPA do nothing at all in this case or does it continue to track after timing changes, just less efficiently than with "legal" training sequence?

I believe DPA run length is the max number of cycles of a constant value can occur before loosing lock. As for a training pattern, I've heard pretty much anything with transitions will work, but with fewer transititons it may just take longer. It is not looking for a pattern though(such as 10-bit comma), just transitions to figure out where the data changes and where to center the clock. There is no word alignment occuring, as that has to be done by you.

--- Quote Start --- As for a training pattern, I've heard pretty much anything with transitions will work, but with fewer transitions it may just take longer. It is not looking for a pattern though(such as 10-bit comma), just transitions to figure out where the data changes and where to center the clock. --- Quote End --- That's what I, too, thought would be logical. However I see different behavior in the field. Sometimes it looks like after achieving initial lock a DPA machine completely stops tracking [very slow in my case] data phase changes. That despite transmitted data containing significant number of transitions.

How can you tell? Do the bits start getting corrupted? How much does your data change?

Understanding training patterns for Stratix-II deserializer DPA

13 Replies

Altera_Forum
Honored Contributor
14 years ago
The DPA is used in lots of applications(ethernet, ADCs, chip-to-chip custom protocols, etc.) I don't know the exact details, but note that you're giving it a clock that matches the source(not phase, but 0PPM difference). It creates basically an 8x oversampling. Unlike a CDR circuit, if there are no edges, this circuit should be able to do nothing rather than drift off.
Out of curiosity, what is the data rate? Do you have an idea how much the data skews?
I agree that I am surely over-simplifying, as everything tends to be more complicated when you peel it back, so make sure you open something with Altera rather than just the forum.
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---

Out of curiosity, what is the data rate? Do you have an idea how much the data skews?
--- Quote End ---

1000 MBps. Uncomfortably close to 1040 MBps maximum specified in the handbook.

No, I have no idea by how much clock/data relationship floats over time and temperature. I thought that it shouldn't be no more than 100-200 ps, but the practice proved me wrong. So I don't try to guess anymore and direct measurements are rather difficult to setup.
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
So from now on I want to rely on exact knowledge.
--- Quote End ---

As far as I understand, you mainly observed the problem, that the receiver isn't stable enough over the intended temperature range. I can't see, how the problem should be related to train patterns or some hidden DPA properties that you suspect.

In my view, is simply a case of operating near the speed limits.

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Understanding training patterns for Stratix-II deserializer DPA

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