Understanding training patterns for Stratix-II deserializer DPA

The DPA is used in lots of applications(ethernet, ADCs, chip-to-chip custom protocols, etc.) I don't know the exact details, but note that you're giving it a clock that matches the source(not phase, but 0PPM difference). It creates basically an 8x oversampling. Unlike a CDR circuit, if there are no edges, this circuit should be able to do nothing rather than drift off.

Out of curiosity, what is the data rate? Do you have an idea how much the data skews?

I agree that I am surely over-simplifying, as everything tends to be more complicated when you peel it back, so make sure you open something with Altera rather than just the forum.