Forum Discussion
Altera_Forum
Honored Contributor
14 years ago --- Quote Start --- I forget all the DPA connections for Stratix II. Some thoughts: - Do you know when the open areas area? Maybe you could disable the DPA from aligning during those periods? (I've heard of people disabling it from changing altogether once it's locked on) --- Quote End --- I don't quite understand what you mean by "open areas". Relative long runs without transitions? No I can't predict them, but with tiny modification of protocol I can assure that they wouldn't happen at all. Don't believe it will make the difference, since they are already extremely rare and certainly much shorter than "DPA run length" from the handbook. As to disabling DPA from changing altogether once it's locked on, that's was our original design. Turned out it is not good enough, although I still don't understand why. In our topology the difference between clock path and data path is in order of 200mm, so, according to my understanding, temperature changes could change the relationship by, at worst, few tens of ps. Nevertheless, the practice proved that the drift is much bigger than that. So now I want fully dynamic solution with DPA tracking all the time. May be, now I went too far into "dynamic" direction. Sort of suffering second-system effect :( However, "fully-dynamic" is a solution that I now want. --- Quote Start --- - Not sure what the transmitter is, but could you add a "comma-character". This doesn't work with some data types, but just a thought. - I have heard of one issue where the design had large variations over temperature, specifically the clock was sent directly to the receive FPGA(running DPA), but went through 3 other FPGAs where the third one was the transmitter. Over temperature, the path through the three FPGAs varied quite a bit(many ns) while the clock path did not. This resulted in a FIFO over-flow in the DPA. I "think" they reset the FIFO once the DPA locked, but can't remember for sure. --- Quote End --- Well, as I said above, our temperature variations a bigger than we anticipated, but hopefully don't exceed 1-1.5 ns. As to reseting FIFO once the DPA locked, according to my understanding of the manual, in Stratix-II that is a default behavior. --- Quote Start --- - Obviously, this shouldn't be happening and it's probably worthwhile filing a Service Request with Altera. --- Quote End --- We are starting. Unfortunately, so far we were not even able to explain to the service person what the problem is. SR process takes time and, at least in my experience, almost never leads to satisfactory results. May be, because I don't tend to ask easy questions that can be answered by re-reading the manuals?