Honored Contributor
Honored ContributorI forget all the DPA connections for Stratix II. Some thoughts:
- Do you know when the open areas area? Maybe you could disable the DPA from aligning during those periods? (I've heard of people disabling it from changing altogether once it's locked on) - Not sure what the transmitter is, but could you add a "comma-character". This doesn't work with some data types, but just a thought. - I have heard of one issue where the design had large variations over temperature, specifically the clock was sent directly to the receive FPGA(running DPA), but went through 3 other FPGAs where the third one was the transmitter. Over temperature, the path through the three FPGAs varied quite a bit(many ns) while the clock path did not. This resulted in a FIFO over-flow in the DPA. I "think" they reset the FIFO once the DPA locked, but can't remember for sure. - Obviously, this shouldn't be happening and it's probably worthwhile filing a Service Request with Altera.
