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Thank you ted for confirming that my idea of how it works is roughly correct, regarding the avalon master to read from the sdram controller :
the controller has a datawidth of 16 bits but how I understand it is that I can set a datawidth of 32 bits on the avalon master,
would set the starting address of sdram controller base address + start of the 64 byte block I want to read (that needs to be a byte alligned address, not aligned to the sdram datawidth 16 bits, right?),
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That depends on what you have set the addressUnits property in your _hw.tcl to. See mnl_avalon_spec.pdf it explains this a bit.
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set a burstcount of 16 and byteenable to 4,
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byteenable is a bitmask so '4' won't do what you hope it would. again, see mnl_avalon_spec.pdf
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start via asserting avalon master read and everytime data is available from the sdram controller the readdatavaild signal would be asserted for one clock cycle.
So I just have to look for the readdatavalid signal of the sdram controller and can than read the complete 32 bit word and store it internally.
After receiving all the data I just deassert the master read signal.
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The command is accepted when read=1 and waitrequest=0 for one clock period. So you would deassert read right after you saw that waitrequest hadn't been asserted. Then wait for 'readdatavalid'. After you've received the full count of 'readdatavalid' qualified transactions, the sequence is over.
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