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It all sounds roughly correct and of course there are a lot of little details you need to get correct. I'm not sure what you envision as your test and development environment, but I can recommend getting started with the Avalon BFM's in simulation sooner rather than later, but you might find using the System Console to issue reads and SignalTap to debug might be easier if you're just learning things.
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Thank you ted for confirming that my idea of how it works is roughly correct, regarding the avalon master to read from the sdram controller :
the controller has a datawidth of 16 bits but how I understand it is that I can set a datawidth of 32 bits on the avalon master,
would set the starting address of sdram controller base address + start of the 64 byte block I want to read (that needs to be a byte alligned address, not aligned to the sdram datawidth 16 bits, right?),
set a burstcount of 16 and byteenable to 4,
start via asserting avalon master read and everytime data is available from the sdram controller the readdatavaild signal would be asserted for one clock cycle.
So I just have to look for the readdatavalid signal of the sdram controller and can than read the complete 32 bit word and store it internally.
After receiving all the data I just deassert the master read signal.
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