Unable to simulate MAX 10 ADC

Hi,

I'm thoroughly stuck on simulating the MAX 10 ADC.

Tools: Quartus 17 Lite (and 16.1) + ModelSim-Altera 10.5b

Modelsim error:

# ** Error: (vsim-3033) C:/temp/ADCtest3/source/On_Chip_ADC/simulation/submodules/On_Chip_ADC_modular_adc_0.v(38): Instantiation of 'On_Chip_ADC_modular_adc_0_control_internal' failed. The design unit was not found.

Steps taken:

1. Create Max10 project with top level and testbench VHDL.

2. Use IP Catalog to create "Altera Modula ADC Core" and generate the HDL code, selecting VHDL synthesis and VHDL models.

3. Add the generated component to my VHDL

4. Add the generated .qip and .sip files to Project Navigator

5. Tools>Run Simulator Tool>RTL Simulation

6. Get several ModelSim error messages similar to the above.

I'm puzzled that I don't see 'On_Chip_ADC_modular_adc_0_control_internal' defined anywhere.

Does anyone know what causes this error?

(I'm using the IP Catalog, not Qsys, because I want to be able to wire up the ADC PLL myself. I do have the PLL.)

Thanks,

Rob