Forum Discussion
Altera_Forum
Honored Contributor
7 years agoHi,
I had the same issue few month ago. There are mistakes in Altera simulation model (regarding module's naming) and I simply linked the synthesis model in my simulation and it worked. Source the files C:/temp/ADCtest3/source/On_Chip_ADC/synthesis/... instead of C:/temp/ADCtest3/source/On_Chip_ADC/simulation/... Excelsium