Unable to meet timing requirements for 180 MHz Source-Synch. DDR Interface due to PLL uncertainty

Hi,

Correct me if I understand wrongly. ADC_2CH_CLKOUT and ADC_1CH_CLKOUT are the output clock from the ADC and these two clocks will be shifted by 90 degree using the PLL. If this is the case, you have to use create_clock to constrain ADC_2CH_CLKOUT and ADC_1CH_CLKOUT but not create_generated_clock because you have an input port assigned to it. Besides this, the false path and multicycle constraints are applied between the virtual clock and data clock. In your latest sdc, you have applied the constraint between adc1ChDataClock_virt and adc1ChClockout. This is correct only if you are using adc1ChClockout to latch the data. You have to use the generated clock from the PLL in the false path and multicycle assignment if you are using the PLL shifted clock to latch the data.

Thanks.

Best regards,

KhaiY