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JeDi's avatar
JeDi
Icon for New Contributor rankNew Contributor
5 years ago

Unable to meet timing requirements for 180 MHz Source-Synch. DDR Interface due to PLL uncertainty

Dear all, My current project involves an interfacing between an ADC, clocked at 180 MHz with source-synchronous DDR LVDS outputs, and a Cyclone V FPGA (5CSXFC6). To start, I instantiated a ALTDDI...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


There are missing files in the attachment. You may provide the design.qar by clicking on Project > Archive Project > Archive


Error (12006): Node instance "systempll_inst" instantiates undefined entity "systemPll_0002"

Error (12006): Node instance "adcpll_inst" instantiates undefined entity "adcPll_0002"

Error (12006): Node instance "adcpll_inst" instantiates undefined entity "adcPll_0002"


Thanks.

Best regards,

KhaiY


  • JeDi's avatar
    JeDi
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hi all,

    I didn't know about the archive function, sorry. Hopefully it works this time.

    Currently the PLL output clocks are used as the clock inputs to the receivers, this can be changed here:

    inclock => adc2ChClkout_90deg,
--inclock => ADC_2CH_CLKOUT,

    Thank you!