unable to create symbol file for current file (Verilog HDL file) in Quartus IIweb13.1

Hi,

I am also doing that tutorial and I have the same problem. I created a project (just as instructed). Chitranshvarun, were you able to resolve this issue?

Perhaps I should add that I am using this EP4CE6E22C8N FPGA rather than one of the recommended FPGAs...

Thanks in advance,

Chandran