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Altera_Forum
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11 years ago

unable to create symbol file for current file (Verilog HDL file) in Quartus IIweb13.1

Hi, I am unable to create symbol file for current file (Verilog HDL file) in Quartus II web edition 13.1. Compilation report shows 'Data not available'. plz help me !
Altera_Forum's avatar
Altera_Forum
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8 years ago

Hi,

I am also doing that tutorial and I have the same problem. I created a project (just as instructed). Chitranshvarun, were you able to resolve this issue?

Perhaps I should add that I am using this EP4CE6E22C8N FPGA rather than one of the recommended FPGAs...

Thanks in advance,

Chandran