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Honored Contributor
Honored Contributoruart transmitter
Hi there!
I need to decode comands and data sended by device. On the one side I have device with clk, dc, cs and data ports, on the other there is cable uart -> usb. I wrote module to grab data from device and send to the PC. In simulation it works fine, but on the fpga - doesn't. Device sends signals, module grabs them (i think so), but there is no communication on PC (Terminal doesn't print anything). I tried to communicate in the simpliest way - one stop bit, and one start bit. Code is listed below. Does anyone have any suggestion?library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity transmiter is
port(
clk : in std_logic;
dc : in std_logic;
serial_in : in std_logic;
cs : in std_logic;
uart_tx: out std_logic;
lampka_fifo_0 : out std_logic;
lampka_fifo_1 : out std_logic;
lampka_fifo_2 : out std_logic;
lampka_fifo_3 : out std_logic;
lampka_fifo_4 : out std_logic;
lampka_fifo_5 : out std_logic;
lampka_fifo_6 : out std_logic;
lampka_fifo_7 : out std_logic;
data_out : out std_logic_vector (7 downto 0);
cmd_out : out std_logic_vector (7 downto 0);
lampka_dc_indicator : out std_logic;
lampka_clk : out std_logic;
lampka_dc : out std_logic;
lampka_data : out std_logic;
lampka_cs : out std_logic;
lampka_txd : out std_logic
);
end transmiter;
architecture transmiter_arch of transmiter is
signal data_bus : std_logic_vector (7 downto 0);
signal counter_reg : integer range 0 to 7 := 0;
type fifo is array (0 to 7) of std_logic_vector (7 downto 0);
signal fifo_buf : fifo;
signal data_to_be_send : std_logic_vector (7 downto 0) := "00000000";
signal fifo_deep : integer range 0 to 10 := 0;
signal ready_to_send : std_logic;
signal dc_indicator : std_logic;
signal dc_indicator_reg : std_logic := '0';
begin
process (clk)
begin
if rising_edge(clk) then
if (counter_reg = 7) then
counter_reg <= 0;
else
counter_reg <= counter_reg + 1;
end if;
end if;
end process;
process (clk)
begin
if (rising_edge(clk)) then
for i in 0 to 6 loop
data_bus(i+1) <= data_bus(i);
end loop;
data_bus(0) <= serial_in;
end if;
end process;
write_to_fifo: process (clk)
begin
if (clk = '1') then
if (counter_reg = 0) then
fifo_buf(fifo_deep) <= data_bus;
fifo_deep <= fifo_deep + 1;
end if;
if (dc = '1') then
data_out <= data_bus;
else
cmd_out <= data_bus;
end if;
else
if (fifo_deep > 0 and ready_to_send = '1') then
data_to_be_send <= fifo_buf(0);
for i in 0 to 6 loop
fifo_buf(i) <= fifo_buf(i+1);
end loop;
fifo_deep <= fifo_deep - 1;
data_to_be_send <= fifo_buf(0);
end if;
end if;
end process;
send : process (clk)
variable send_cnt : integer range 0 to 10 := 0;
begin
if (rising_edge(clk)) then
if (send_cnt = 0) then
uart_tx <= '0';
lampka_txd <= '0'; -- !!!!!!!!!!!!!!!!!!!!!!!!
send_cnt := send_cnt + 1;
ready_to_send <= '0';
elsif (send_cnt > 0 and send_cnt <9) then
uart_tx <= data_to_be_send (send_cnt - 1);
lampka_txd <= data_to_be_send (send_cnt - 1);
send_cnt := send_cnt + 1;
ready_to_send <= '0';
elsif (send_cnt = 9) then
uart_tx <= '1';
lampka_txd <= '1';
send_cnt :=0;
ready_to_send <= '1';
end if;
end if;
end process;
process (cs)
begin
if (rising_edge(cs)) then
dc_indicator_reg <= not dc_indicator;
end if;
end process;
dc_indicator <= dc_indicator_reg;
lampka_cs <= cs;
lampka_data <= serial_in;
lampka_clk <= clk;
lampka_dc <= dc;
lampka_dc_indicator <= dc_indicator;
lampka_fifo_0 <= fifo_buf(0)(0);
lampka_fifo_1 <= fifo_buf(0)(1);
lampka_fifo_2 <= fifo_buf(0)(2);
lampka_fifo_3 <= fifo_buf(0)(3);
lampka_fifo_4 <= fifo_buf(0)(4);
lampka_fifo_5 <= fifo_buf(0)(5);
lampka_fifo_6 <= fifo_buf(0)(6);
lampka_fifo_7 <= fifo_buf(0)(7);
end transmiter_arch;
