Forum Discussion
Altera_Forum
Honored Contributor
13 years agoThere isn't quite enough here to go on, but I'll hazard a guess. The code for uart1 is critical.
If the isTransmitting signal is generated using a clocked process, (sorry for the terminology, I'm a VHDL guy) the isTransmitting signal will go high at least 1 clock after begin_transmit is set high. This will cause if(!isTransmitting) to be true. A Verilog simulator would probably show you exactly what is going on. If you are still stuck on this, post the uart code. It will help fill in the gaps.