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Altera_Forum's avatar
Altera_Forum
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14 years ago

Uart data ready

Hi all,

I am periodically sending data from LabView to my cycloneIII development kit (bemicro) and I want to check if there is data available to be read in NIOS II. Unfortunately, I have not been able to use the data ready bits, can someone enlighten me on how to do this?!

Do I need to use

ALT_UART_READ_RDY 0x1

or

ALTERA_AVALON_UART_CONTROL_RRDY_MSK (0x80) ?

If yes, how am I supposed to do so? Any help would be appreciated!

marek

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  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    On more thing, I added the following line to intialize the CONTROL register. The problem is still the same though...

    IOWR_ALTERA_AVALON_UART_CONTROL(UART_BASE, 0);
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Ah aH :-)

    (You can enclose your code with 
     ...
    )

    Try 

    if (IORD_ALTERA_AVALON_UART_STATUS(UART_BASE) & ALTERA_AVALON_UART_STATUS_RRDY_MSK) // be coherent
{
status = IORD_ALTERA_AVALON_UART_STATUS(UART_BASE); // status=64 means "TRDY=1" and that is normal.
// IOWR(UART_BASE,0x01, status);
IOWR_ALTERA_AVALON_UART_TXDATA(UART_BASE,status); // status is 16-bit wide , OK
}

    For reference , http://www.altera.com/literature/ug/ug_embedded_ip.pdf (UART CORE REGISTER MAP en page 79)

    I may laugh if since the beginning, your are looking for the wrong register bit : trdy instead of rrdy :-d

    My teacher would says "Fatal Error" and give 0 point to the whole exam ! :-)

    On an other side,

    # include "system.h" // doesn't mean that system.h matches to SOPC, even if system.h exists and makes no software build error.

    You could have an working system.h but very old and not matching.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hey,

    Yes, I should have explained what I'm trying to do. This was for debugging purposes, I write the status to the UART to visualize it on the PC and see if the RRDY bit ever goes high when sending data.

    The if statement was just added because the NIOS was firing too quickly, thus the status is written to the uart when transmit is ready.

    The problem remains the same, RRDY never goes high even though data is sent through the UART...
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    System.h is up to date, I regenerated the SOPC, compiles the quartus project and regenerated the BSP.

    It remains that I continuosly read status=64 (TRDY high) when I expect 128 (or more, RRDY high) indicating that there is data ready to be read on the UART...
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    When a new character is

    fully received via the RXD input, it is transferred into the rxdata register, and the

    status register's rrdy bit is set to 1

    --- Quote End ---

    Are you sure that data come from Labview to your UART ? cable problem ?

    Did you spy the RX-line of your UART ? See something (use a scope)

    To be continued :-)
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Ok. The code is finally working! The read ready interrupt (in the control register) must be disabled first, otherwise the RRDY mask does not display the proper value. I used the following command to disable the interrupt:

    IOWR_ALTERA_AVALON_UART_CONTROL(UART_BASE, 0);