Forum Discussion
JCarr18
New Contributor
New Contributortype mismatch for generic 'integer_values' (Mixed language design)
Hello, I have a mixed-language design where I would like to instantiate a VHDL module in a Verilog file. The module has the following definition: entity vhdl_module is
generic (
integer_values: w...
Vicky1
Regular Contributor
Regular ContributorHi Javier,
I feel, It may not be available in Verilog since you are using array of integers.
Could you please check it in system Verilog?
Regards,
Vikas
JCarr18New Contributor
New ContributorHi Vikas,
How can I switch my verilog file to System Verilog? is there any way to define a code section as System Verilog (i.e. the module instantiation)? Thanks in advance.
Regards,
Javi
