Contributor
Super ContributorThe easiest way to check is to use Interface Planner, assuming you are using the Pro edition of Quartus Prime. In that tool, you can see exactly what legal locations are available for your interfaces as you place them and get a Tcl script that will automatically set up the required location assignments.
If you're using Standard edition, you can place the interfaces as you want and then run I/O Assignment Analysis to check your placement without having to run a full compilation of the design. This will be more time consuming because it may require multiple iterations to find a valid placement, but it will get you to a placement solution.
For information on Interface Planner if this is available to you, see this online training:
https://www.intel.com/content/www/us/en/programmable/support/training/course/oblueintro.html
ContributorHi,
Thanks for the suggestion with Interface planner.
I found the problem.
As we are placing the EMIF controller in a common I/O column, Need to use same PLL reference clock & reset to both the controllers.
Also, I am using Quartus 18.1 version & it has a known issue as mentioned in the below link.
https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/emif/2019/error-13149---emif-phylite-systems-sharing-a-pll-reference-clock.html
After using same clock for both the controller's PLL ref clk input & applying the work around I am able to complete the fitter & able to get the pin out from Quartus. It is mapping the pin outs to IO banks from 3A to 3H.
With regards,
HPB
ContributorHi,
I checked in Quartus 20.3 version.
This issue is not yet resolved. I am seeing same issue with latest Quartus version. But If I apply the work around, the compilation with 2 controller is successful.
What will be the impact of the work around?
With Regards,
HPB
ContributorHi,
Any update on the issue @ 20.3 version?
What will be the impact of the work around?
With Regards,
HPB
