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Rk_Athram's avatar
Rk_Athram
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

TTK failed reading from PHY slave, when PCIe and transceivers used in same project

Hi, We are using PCIe and Transceivers in our project. we have tested both separately for transceivers and PCIe. We are able to access transceivers In separate project by using transceivers tool...
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

HI,


From the error message, it's basically complaining about either you didn't provide reconfig_clk from your board or the transceiver is not released from reset properly.

  • Can you double-check your reconfig_clk (100MHz to 125MHz) and verify your transceiver power-up sequence to ensure calibration is done and both PCS Tx_ready and Rx_ready signal are asserted ?
  • Pls share with me your signal_tap file where you captured all the transceiver status signals from Transceiver PHY reset controller IP
  • Another thing to watch out is did you provide clock frequency to FPGA clkusr pin as transceiver power-up calibration clock ?
  • Another suggestion is pls reduce/disable your JTAG connection chain on board and also reduce the JTAG clock frequency from 24MHz to maybe 16MHz or 6MHz to see if it helps
  • Please ensure the reconfig_clk and reconfig_reset of the transceiver PLL were connect to system clock and reset


Regards,

WeiChuan_C_Intel