TSE_MAC Timing Contraints

I have moved (re-posted) this topic in the IP forum. Link below

http://www.alteraforum.com/forum/showthread.php?p=133368#post133368

Hi Guys,

I'm using 2x DE2-115s with my own Ethernet design (RGMII) and i'm suspecting i'm getting timing issues. I have no real idea on how to set up constraints and i'm just trying to patch something together and i need some help.

what i think i have figured out so far.......

I have two primary sources for my info:

- The tse_mac manual (attached a screenshot of relavant page to post)

- The DE2-115 webserver example

Now the Webserver example doesn't include the TSE_MAC timing constrains sdc file. It includes its own SDC file which has the lines:

 
create_clock -period 8 -name "ENET0_RX_CLK" 
set_input_delay  -clock "ENET0_RX_CLK"  -min 2  

For its interface signals to the FPGA pins on the top level it has this below. (MY DESIGN USES THESE ASWELL):

 //////////// Ethernet 0 //////////
 ENET0_GTX_CLK,
 ENET0_INT_N,
 ENET0_LINK100,
 ENET0_MDC,
 ENET0_MDIO,
 ENET0_RST_N,
 ENET0_RX_CLK,
 ENET0_RX_COL,
 ENET0_RX_CRS,
 ENET0_RX_DATA,
 ENET0_RX_DV,
 ENET0_RX_ER,
 ENET0_TX_CLK,
 ENET0_TX_DATA,
 ENET0_TX_EN,
 ENET0_TX_ER,
 ENETCLK_25,

The TSE manual (page 28, see attached screenie) on the other hand discusses the generated sdc file and how you have to rename signals.

The default being:

 #  *************************************************************#  Customer modifiable constraints, value is set default by constraints#  *************************************************************#  Hierarchical path to the TSE
set SYSTEM_PATH_PREFIX ""#  Frequency of network-side interface clocks or reference clocks
set TSE_CLOCK_FREQUENCY "125 MHz"#  Frequency of FIFO data interface clocks
set FIFO_CLOCK_FREQUENCY "100 MHz"#  Frequency of control and status interface clock
set DEFAULT_SYSTEM_CLOCK_SPEED "66 MHz"    #  Name the clocks that will be coming into the tse core named changed from top level   
set  TX_CLK             "tx_clk"                        
set  RX_CLK             "rx_clk"                        
set  CLK                "clk"
set  FF_TX_CLK          "ff_tx_clk"
set  FF_RX_CLK          "ff_rx_clk"
set  TBI_TX_CLK         "tbi_tx_clk"
set  TBI_RX_CLK         "tbi_rx_clk"
set  REF_CLK            "ref_clk"

I need help to set mine up correctly. Below is the details of my design we many need to know.

-------------------------------------------------------------------------------------------

I am feeding my TSE_MAC with botha firmware data path and a Nios datapath through MUX and DeMUX

My Nios is running at 100Mhz.

As pictured my TSE_MAC is running all 3 clocks at 50MHz.

so what exactly do i do here?

From what i can gather i imagine i have to (please correct me if wrong)

1. I would have to change the generated SDC file to have 50Mhz for each of the clocks? all 3?

2. Rename the tx and rx clocks to have "ENET0_" prefix to match my top level signals.

3. what about the other signals in that sdc?

4. Do i then run the TCL? i think i did this and it overwrote my changes to the sdc.

5. Add this sdc file to my timing constraints files in the assignment editor.

6. Compile?

Other questions:

• Do i need to include the other auto generated TCL files that seem to be generated by SOPC. There is one with my SOPC design name.

• Notice the terasic design doesn't use any of this. Is it a case of theres being a short cut and i shouldn't do both its method and the TSE manual one? or both?