Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Trying to implement SPI slave in Cyclone IV - why this isn't working?

Hi, i'm trying to implement some practical stuff in Cyclone IV. For a start i need SPI slave which will write data received from master to dual port RAM. I'm struggling with basics in SPI receiver code (not much FPGA and HDL experience).

When receiving a byte from SPI master, i want to send back an anternate bit pattern on MISO, triggering MISO state change on a negative edge of the SPI clock. This is not working as expected, as can be seen on attached oscilloscope screenshot. There is something happening at the negative edge of the clock, but it's not a proper state change, jus some miniscule impulse that is immediately shut down back to 0. Of course master reads this received byte as 0x00. Code is synthesized as on attached image. I/O standard for all of the pins is defined as 3.3V LVCMOS.

https://alteraforum.com/forum/attachment.php?attachmentid=15067&stc=1

https://alteraforum.com/forum/attachment.php?attachmentid=15065&stc=1

https://alteraforum.com/forum/attachment.php?attachmentid=15066&stc=1 


module spi_recv 
(
    input sclk, mosi, cs,
    output miso,
    output reg  output_byte,
    output reg  mem_addr,    
    output memclk,
    output mem_we
);
reg  bit_counter;
reg  memcell_counter;
always @(negedge sclk)
  begin
     miso <= ~miso;      
  end
    
 endmodule

As even this is not working as expected, i have stripped the rest of code suspecting that there is some problem in it (still no change).

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    7 years ago

    Is the code you've posted the source for this or the schematic? The schematic is missing the inverter in the Q -> D feedback path - something you have included in your code.

    In the code you've not explicitly declared that the output signal 'miso' is a register. Try changing that to:
      output reg miso,
    If the schematic is what Quartus has interpreted your code to be then I think we have the answer - no inverter.

    If the schematic is your source, add the inverter.

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    7 years ago

    As you can see it in the RTL view, MOSI signal is not binded.

    Your code tries to invert the output signal in the output signal, you never use the input signal.

    To make a very simple inverted loopback, you should invert the mosi signal.

    miso <= ~mosi;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    7 years ago

    Hi, attached code is the source for attached schematic. This is exactly how Quartus is synthesizing attached code (schematic is from RTL viewer in Quartus). Isn't the circle on D input a sign that it should invert the signal? I have changed MISO declaration to reg, but nothing changed in behavior of the circuit. In response to JRL - i have stripped entire SPI receiver code, and left only this part which i have attached. I would like to understand why this small part is not working (it should output 01010101 on MISO, MISO change should be triggered by falling edge of input clock, MOSI is not used here).

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    7 years ago

    The schematic fits the code, yes the circle at D is the inversion operation, but the oscilloscope waveform can't be related to it at all. There's obviously a second FF involved to achieve 4:1 frequency division.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    7 years ago

    I have rewritten this module so that it's clocked with higher frequency PLL instead of SCLK, and it works ok now.