Trying to implement SPI slave in Cyclone IV - why this isn't working?

Hi, attached code is the source for attached schematic. This is exactly how Quartus is synthesizing attached code (schematic is from RTL viewer in Quartus). Isn't the circle on D input a sign that it should invert the signal? I have changed MISO declaration to reg, but nothing changed in behavior of the circuit. In response to JRL - i have stripped entire SPI receiver code, and left only this part which i have attached. I would like to understand why this small part is not working (it should output 01010101 on MISO, MISO change should be triggered by falling edge of input clock, MOSI is not used here).