True Dual Port Ram Synthesizes error with two clock signals

Reviewing the thread, I see, that up to the middle, every reported issue has turned out as case of effectively operating the RAM in an incorrect way or some basic logic design error. Also considering a learning curve, it seems most likely that we still have something similar, possibly less obvious. Of course, an additional hardware issue would be possible though. Everything can be found out by intelligent utilization of debugging methods, particularly Signal Tap.