Trouble with EMAC on CycloneV SoC

Timequest reports the timing path based on your timing constraint.

In 14.0, there is a fix in this timing path from HPS EMAC to FPGA region but the SDC is yet to be updated.

During GMII mode, the clock is source from EMAC Clk Manager to PHY.

You should take note on your timing constraint, the clock node should be source from internal node as below:

soc_system_hps_0_fpga_interfaces.sdc

create_clock -name <clock_name> -period <clock_period> [get_keepers {*|fpga_interfaces|peripheral_emac0~internal_clock}] -add

<clock _period> refer to tx clock rate of GMII interface.

old timing constraint to be removed:

create_clock -period <clock_period> [get_pins -compatibility_mode *|fpga_interfaces|peripheral_emac0|phy_txclk_o]