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Altera_Forum
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11 years ago

Trouble Getting DDR SDRAM Working in Qsys

Hello, I'm making a board with a Cyclone IV FPGA, and having some trouble getting my DDR signals to be what they should be. I have a clock bridge between a Nios II Processor and my DDR SDRAM co...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Before you consider the internal logic - how confident are you in your hardware? Are you happy the board has been assembled correctly? Do you have experience putting such an FPGA design together, using the IP you mention?

To confirm your design and build you might try putting together a much simpler design which just attempts to toggle some of the relevant pins so you can monitor the connections to the external memory. Once you're happy that your hardware platform is correct we can consider using something more useful.

Regards,

Alex